1). Field of the Invention
The present invention relates generally to semiconductor packaging.
2). Discussion of Related Art
FIG. 1 of the accompanying drawings illustrates a prior art semiconductor package 10 which is in the form of a multichip module. The semiconductor package 10 includes a package substrate 12 and first and second integrated circuits, 14 and 16 respectively, mounted to the package substrate 12 by an array of bumps 18 or the like.
The package substrate 12 includes a number of insulative layers 20 with a layer of metal lines 22, a sheet metal grounding layer 24 and a sheet metal power supply layer 26 sandwiched between the respective insulative layers 20.
In order to test the semiconductor package 10 or in order to mount the integrated circuits 14 and 16 to the package substrate 12 it may be required to heat the semiconductor package 10 to a temperature sufficient for testing purposes or to a temperature sufficient to cause reflow of the material of the bumps 18. The material of the insulative layers 20 may be a material such as a polyimide which creates a gas or gasses when being heated. Severe distortion and delamination of the layers of the package substrate 12 may occur if these gasses become trapped between the layers of the package substrate. In order to provide for outgassing of these gasses a number of openings 28 are formed in the grounding and power supply layers 24 and 26. The gasses escape from between the layers of the package substrate 12 and collect within the openings 28 thereby preventing distortion or delamination of the layers of the package substrate 12.
FIG. 2 is a plan view illustrating one of the metal layers 24 or 26 and the metal lines 22A, B, C, D, E. The metal lines 22A, B, C, D, E extend parallel to one another from one side to an opposing side of the package substrate 12 parallel with the metal layer 24 or 26. The openings 28 are located within the substrate so that three of the metal lines (22A, B, and C) pass over the openings.
FIG. 3 is a view similar to FIG. 2 wherein the metal lines 22A, B, C, D, E are shown in phantom lines in a plane of the grounding layer 24.
Referring again to FIG. 1, each integrated circuit 14 and 16 includes semiconductor electrical elements, 32A, B . . . and 36A, B . . . respectively, formed therein that may be transistors, capacitors, diodes or any other electrical elements. It is assumed, for purposes of discussion, that each of the electrical elements 32A, B . . . in the first integrated circuit 14 is connected to a respective metal line 22A, B, C, D, E and that each of the electrical elements 36A, B . . . in the second integrated circuit 16 is also connected to a respective metal line 22A, B, C, D, E and that each electrical element 32A, B . . . in the first integrated circuit 14 switches a respective electrical element 36A, B . . . in the second integrated circuit 16 by transmitting a signal through a respective metal line 22A, B, C, D, E.
Each electrical element 32A, B . . . and 36A, B . . . is also connected to both the grounding layer 24 and to the power supply layer 26. When the electrical elements 36A, B . . . in the second integrated circuit 16 are switched, return currents pass through the grounding layer 24 back to the electrical elements 32A, B . . . in the first integrated circuit 14.
The switching signals from the electrical elements 32A, B . . . in the first integrated circuit 14 through the metal lines 22 A, B, C, D, E to the electrical elements 36A, B . . . in the second integrated circuit 16 are indicated by the arrows 42 in FIG. 2.
The return currents from the electrical elements 36A, B . . . in the second integrated circuit 16 to the electrical elements 32A, B . . . in the first integrated circuit 14 are indicated by the arrows 46 in FIG. 3.
At high frequencies the return currents 46 tend to follow the paths of least inductance which tend to be localized below the respective metal lines 22A, B, C, D, E. However, since the metal lines 22A, B and C pass over the openings 28, the return currents 46 corresponding to the metal lines 22A, B, and C are diverted around the openings 28.
Due to diversion of the return currents 46 a measure of interference or "crosstalk noise" occurs between some of the return currents 46 (see for example the return currents 46 corresponding to the metal lines 22B, C and D).
Crosstalk noise between the return current 46 may affect the respective switching signals 42 relative to one another. High levels of crosstalk noise may even result in the switching signals 42 being so dramatically affected that incorrect switching of the electrical elements 36A, B . . . in the second integrated circuit 16 results, and is thus undesirable.
It can also be seen from FIG. 3 that the return signals 46 which are diverted around the openings 28 follow a longer path. By following a longer path, some of the return signals 46 may be delayed relative to one another, which, in turn, may result in delay in switching of the switching signals 42 relative to one another. Delay in the switching signals 42 relatively to one another results in "clock skew" in the switching of the electrical elements 36A, B . . . in the second integrated circuit 16. For example, should two or more of the electrical elements 32A, B . . . in the first integrated circuit 14 be clocked to simultaneously switch and therefore simultaneously transmit the switching signals 42, a delay would occur in switching one of the electrical elements 36A, B . . . relatively to switching of another of the electrical elements 36A, B . . . in the second integrated circuit.
A longer return signal will generally result in an increase in inductance (L). Inductance (L) can therefore be used as a measure for comparing delay of the return signals.
Furthermore, capacitances between the metal lines 22A, B, C, D, E and the grounding and power supply layers 124 and 126 also affect delay of the return signals. A decrease in capacitance (C) of a respective metal line 22A, B, C, D, E will generally result in less delay of the return signals.
Characteristic impedance can therefore be expressed by the formula: EQU Characteristic Impedance=L.sub.s +L /C.sub.s +L where
L.sub.s is self inductance; and PA1 C.sub.s is self capacitance.
A higher characteristic impedance will generally result in more delay.